by Max Fuchs, Technische Universität München
In comparison to combinatorial circuits, sequential ones store values by means of various kinds of flipflops. The basic flipflop which is used in some way by all flipflops is the RS flipflop.
The behaviours of an RS-flipflop is well known at least for standard inputs set, reset and hold. However, for setting and resetting an RS-flipflop simultaneously or even applying a hold right after the former one ( irregular input sequence), the output behaviour is often unclear. This problem has been tackled and a concise answer by means of adequate models at the RTL and the Gate level has been given. At the RTL a black box specification is presented in a tabular form. At the Gate level an equational definition of a corresponding network is outlined.
The formal framework the modeling has been carried out in FOCUS [Broy et al. 91], a design method for distributed systems based on streams and stream processing functions.